## Projektovanje VLSI

- Detalji
- Kategorija: Osnovne akademske studije

VII semester (izborni premet)

Goal: Adoption and systematization of knowledge related to the design of Very Large Scale Integrated (VLSI) circuits.

Outcome: Getting competence for designing of Very Large Scale Integrated (VLSI) circuits based on VHDL.

Classes:

1. Introduction to VLSI and VHDL. World of integrated circuits. Application specific integrated circuits. Field programmable gate array. Top level ASIC digital design flow. Modeling the digital systems. Domains and levels of modeling. Levels of design description. VHDL language for digital circuit design. VHDL design styles: dataflow, structural, behavioral. Entity declarations, architecture body, dataflow descriptions, behavioral descriptions, structural descriptions, test benches.

2. Behavioral high level modeling. Behavioral synthesis. High-level system modeling in VHDL. An example of non-synthesizable behavioral VHDL code of Stop-Band IIR filter, from mathematical equations to high-level simulation; fixed point representation of filter coefficients. Experiments with different arithmetic precision of filter coefficients in VHDL in high-level simulation. Definition of packages in VHDL. Defining types in VHDL. Creating complex test benches.

3. VHDL synthesis, Non synthesizable VHDL code. Different descriptions of edge sensitive flip flops. Rules for synthesis of combinatorial logic. Examples of incomplete sensitivity list. Rules for synthesis of sequential circuits. Synthesis constraints, user defined attributes, area and structural constraints, resource constraints. Timing constraints. Synthesis for FPGA.

4. ADDERS in VLSI. Bit-Serial and Ripple-Carry Adders, Carry-Look ahead Adder, Prefix Computation, Ladner-Fischer, Brent-Kung Carry Network, Kogge-Stone Carry Network, Carry-Skip Adders, Carry-Select Adders.

5. Multipliers in VLSI. Combinatorial parallel NxN multiplier based on N-bit Ripple Carry Adders. Combinatorial parallel NxN multiplier based Modified FA cells. Sequential circuit Booth multiplier. Sequential multiplication circuit based on Shift/Add Algorithm. Theory and detailed explanation, from schematic to VHDL code.

6. Timing in Synchronous Systems. Combinational or sequential circuit. Clock signal. Timing characteristics of combinatorial circuits. Timing characteristics of sequential circuits. Setup time. Hold time. Minimum clock period. Review: Synchronous timing basics, positive clock skew, negative clock skew, clock jitter, combined impact of skew and jitter, clock distribution networks, balanced and H-tree clock networks, problems of clock trees dissipation.

7. Timing in Asynchronous Circuits, Asynchronous circuits. Benefits of asynchronous circuits. Disadvantages of asynchronous circuits. Event logic Muller C element. Handshake Communication. Two phase handshake protocol. Four Phase handshake protocol. Globally asynchronous locally synchronous design.

8. Microcontroller design. Computer essentials. Von Neumann and Harvard computers. Controller/datapath partitioning. Instruction execution sub-operations. Assembler instructions & machine code. Direct/immediate addressing modes. Design of subsystems: the principle

pipelining. Datapath. Control path. The basic datapath subsystems (combinational shifters, adders, ALU, multipliers, memories.

9. Low Power Design in VLSI. Reasons for low power. Power impacts on system design. Low power strategies. Power dissipation in CMOS. Sources of power dissipation. Switching power dissipation. Short circuit power dissipation. Leakage power dissipation. Methods for power reduction. Balancing operations. Carry ripple. Resource sharing. Operating at the lowest possible voltage. Architecture trade-offs. Parallel data path. Pipelined data path. Power down techniques. Power analysis in the design flow. Low-power synthesis.

10. Digital layout design. Cadence tools: RTL Compiler and SoC Encounter. RTL synthesis. Layout implementation. Floor planning. Placement of standard cells. Routing (route power, ground signals, clock tree synthesis/routing, global and detailed routing of signal nets). Clock insertion. Functional and formal verification. Parasitic extraction. Timing analysis.

11. Circuit's faults modeling, Verification and testing. Reasons to model faults. Functional tests. Structural testing. Common fault models. Static faults transistor. Open and short faults memory faults PLA. Delay faults. Single stuck-at fault. Test generation for three-input NAND gate. Positive and negative re-convergence. Transistor faults. Stuck-open example. Stuck-short example. Basic principle of IDDQ testing. (ovo poglavlje predaje Miljana).

12. Example of simulation of stuck-at faults in ADDER circuit. Simulation of stuck-at defects in 4-bit ADDER circuit. The ADDER circuit is comprised of Full-Adder gates. One Full Adder gate is comprised of NAND and INV logic gates. Simulation of stuck-at faults at gate input and output ports. Else, set of testing vectors that covers as many faults as possible. (ovo poglavlje predaje Miljana).

Exercises:

1. Recapitulation - VHDL descriptions of basic combinatorial circuits (part 1): VHDL code examples of AND, OR, INVERTER gates. Example of VHDL code of complex combinatorial logic: the structured and dataflow approach. Complex VHDL expressions. Generics used for delay modeling. An example of Test-bench for simple combinatorial circuit verification.

2. Recapitulation - VHDL descriptions of basic combinatorial circuits (part 2): An example of three-state circuit using when-else VHDL construct, an example of Decoder circuit using when-else VHDL construct, an example of 7- segment decoder using with-select VHDL construct, 4-to-1 multiplexer circuit using with-select VHDL construct, 4-to-1 Multiplexer circuit using when else VHDL construct, Structural code of 4-to-1 multiplexer circuit based on three–state circuits, Priority encoder circuit using sequential VHDL coding – processes, FULL ADDER circuit dataflow description, Structural VHDL code of ADDER circuit based on FA.

3. Recapitulation - VHDL descriptions of basic sequential circuits: SR latch, level sensitive memory device, D Flip flop with asynch. reset, D Flip flop with synch. reset, D Flip flop with synch. enable signal, T Flip flop with asynch. reset, Generics used for register length modeling, register with asynch. reset, VHDL code of shift register, VHDL code of counter, ROM memory, RAM memory, an example of Finite State Machine.

4. Project 1, Design of synthesizable 16-bit Carry look ahead adder. After creating the VHDL code, the adder is verified by simulations. After that, implementation on Altera DE1 board follows.

5. Multiplier circuits: Synthesizable combinatorial parallel NxN multiplier based on N-bit Ripple Carry Adders. Detailed explanation, from schematic to VHDL code. Project is verified using Altera DE1 board.

6. Project 2, Multiplier circuits: Synthesizable combinatorial parallel NxN multiplier based Modified FA cells. Based on given schematic, the student must implement VHDL code, including test-bench for logical verification.

7. Multiplier circuits: Synthesizable sequential circuit Booth multiplier. Detailed explanation. Design of modified Booth multiplier, from schematic to VHDL code, including test benches. Projects is verified using Altera DE1 board.

8. Design the sequential circuit Booth multiplier in ASIC. Cadence tools: RTL Compiler and SoC Encounter. RTL synthesis. Layout implementation. Floor planning. Placement of standard cells. Routing (route power, ground signals, clock tree synthesis/routing, global and detailed routing of signal nets). Clock insertion. Functional and formal verification. Parasitic extraction. Timing analysis.

9. Project 3, Multiplier circuits. Design of sequential multiplication circuit based on Shift/Add Algorithm. Detailed explanation is given by lecturers. Based on given schematic, the student must implement VHDL code, including test bench for logical verification.

10. Project 4, Synthesizable IIR filter design: Design of STOP-BAND IIR filter using previously designed multipliers. Theory and detailed explanation is given by lecturer. Use different multiplier circuits (Parallel, Sequential Shift-Add and Booth, etc) for IIR hardware realization.

11. Design the synthesizable simple microcontroller in VHDL. Instruction set contains over 20 assembler instructions that cover data transfer operations (LOAD and STORE instructions), arithmetic operations (ADD and SUB), logical (AND, NOT, OR, XOR), branch instructions (JMP and conditional JMP instructions). Four clock cycle's instruction execution. Possibility to read the single 8-bit input port and to write the output ports. Display the results at 7 segment displays. Supports up to four external interrupts.

12. Project 5. Gain knowledge of RTL system design. Design the synthesizable simple microcontroller in VHDL. Implementation of microcontroller on FPGA board. Students get the VHDL codes of ALU, MAR, PC, ROM, RAM and global schematic. Detailed explanation is given by lecturers. Students need to implement control unit, and put all blocks together in datapath. After that, they verify the MCU VHDL code by simulations using different assembler programs – for multiplication of two numbers, division, square rooting, translation from binary into decimal, etc. Also they write their own assembler programs using given instruction set. Project is verified using Altera DE1 board.